Documentation

Table of Contents

Overview

Synchronization Network Topology
Why SyncESMC

Architecture

Design Goals
Configuration

Configuration Module has two modes:

  1. Static Configuration Mode
    • JSON-based configuration file.
    • System boots up with the predefined configuration
    • Configuration is majorly classified into
      • Device
      • Port
      • Monitoring
  2. Dynamic Configuration
    • REST API
    • Netconf-yang model for O-RAN
Packet Engine

Packet Engine is involved with the interface-related activity.

  • Packet RX
  • Packet TX
  • Port Link up/ Link down Events (Network Link)
  • Packet filtering

Different types of Sockets and interface types are separated using packet engine library.

  • Raw Socket
  • UDS Socket
  • APIs

ESMC State Machine
  • Core of the ESMC stack.
  • Interacts with the Packet Engine, Configuration Engine, HAL.
  • Decides to select the source port based on the Best Port Selection Algorithm (Quality, Priority, Hops).
  • Handles the timer interrupts for Time outs for Hold off time, no activity on the port, Holdover timeout and Restore timers.
  • Interacts with HAL to configure the Hardware.
  1. Packet Engine updates the packet metadata to Database.
  2. Configuration can be updated at run time.
  3. Timer-based events for TX packets, Holdover events, and RX timeout events.
  4. Hardware events like LOS, OOF, PLL Loss.
  5. PLL ID and PLL input selection instructions to HAL.
External MUX for Input Signals
  • Supports Multiplexing, where it can be configured for the maximum number of Sources available for a PLL and the maximum number of inputs which can be given to the PLL.
  • Runs an algorithm to select the best ports and based on priority programs the MUX.
  • Works with any of the available hardware where the number of inputs to PLL is more than the number of sources available. For e.g Broadcom XGS chips for Data Center switches.
Hardware Abstraction Layer
  • Hardware vendors can plugin their HAL functions to integrate with SyncESMC.
  • Ready for Kernel exposed APIs (in future) for controlling the hardware.
  • Hardware interrupt and status monitoring.
  • Multiple vendors’ PLLs can be controlled by the same stack.
External Interface
  • UDS socket can be used to interact with external applications.
    • PTP stack
    • Seamless integration with any PTP stack over a UDS socket.
    • SyncESMC can convert Clock Class to Clock quality as per G.8275.2 Annex F.
  • External Application Interfaces
    • FishEye
    • Configurations